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rdc-19200 monobrid ? series 10-, 12-, 14-, or 16-bit industrial resolver-to-digital converters description the rdc-19200 monobrid series are versatile state-of-the-art resolver-to- digital converters featuring program- mable resolution and bandwidth and a velocity output voltage. resolution programming allows selection of 10-, 12-, 14- or 16-bits and are available with commensurate accuracies up to 2 minutes +1 lsb. resolution programming combines the high tracking rate of a 10-bit con- verter with the precision of a 16-bit device in one package. the velocity output (vel) from the rdc-19200 is a ground-based volt- age of 0 to 10 vdc with a linearity of 2.0%. vel may be scaled up by a sin- gle external resistor to provide up to 10 vdc for the required maximum tracking rate. applications the rdc-19200 series converters are designed for use in modern high performance commercial and indus- trial control systems. applications include motor control, theodolite, radar antenna position information, cnc machine tooling, robot axis con- trol, and process control. with their low cost and superior performance, the rdc-19200 series converters are ideal for motion control and position monitoring applications. features ? low cost ? ideal for motor control ? built-in-test (bit) and loss-of- signal (los) outputs ? velocity output eliminates tachometer ? programmable resolution ? programmable bandwidth ? accuracy to 2.3 arc min. converter high accuracy control transformer gain demodulator error processor vco reference conditioner 16 bit up/down counter 1 lsb antijitter feedback bw u t e vel bw d sin ( q - f ) e sin q cos q mc u t 3 state ttl buffer 3 state ttl buffer ttl buffer bit detect inhibit transparent latch digital interface loss of signal detector 16 bit ct transparent latch 16 bit output transparent latch edge triggered latch digital angle f q t 33 +5v 35 9 inh 5 29 bit 40 ref 30 cb 31 u 32 mc 6 s 8 7 ab 11 el 20-27 bits 9-16 12-19 bits 1-8 10 em 28 los +5v optional inh 50 ns delay u/d 0.4 - 0.7 m s resolution control bw diff gain of 2 diff gain of 2.2 + - 10k 38 signal input +15 37 39 36 1-4 resolver input e vel prog vel -15 v analog conditioner power supply conditioner +11 v v internal dc ref (+5.5 v) +15 34 -15 v gnd ? 1985, 1999 data device corporation ? monobrid is a registered trademark of data device corporation. figure 1. rdc-19200 block diagram note: a / through input or output lines indicates additional functions not shown. see text.
ttl / cmos compatible. pull-up current source to +5 v // 5 pf max cmos transient protected. logic 0 inhibits, logic 1 enables, data stable within 0.3 s. logic 0 enables, data valid within 150 ns. logic 1 high z within 100 ns. logic 0 for control transformer, logic 1 for normal tracking. logic 1 = high bw (530 hz); logic 0 = low bw (130 hz). b (pin 8) a (pin 7 ) 00 01 10 11 unused outputs bits are at logic 0 2 table 1. rdc-19200 specifications these specifications apply over temperature range, power supply range, reference frequency and amplitude range; 10% signal ampl itude variation and up to10% harmonic distortion in the reference parameter value description resolution 10, 12, 14 or 16 bits programmable accuracy grades 8 (1) , 4, 3, 2 (1) minutes max +1 lsb of selected resolution, see ordering information. differential linearity 12, 8 or 4 lsbs in the 16th bit, see ordering information. repeatability 1 lsb max ref input characteristics voltage range single ended input impedance frequency range 4-50 vrms 100k ohm min, 110k ohm nom 360 hz to 6k hz see table 4, dynamic characteristics. digital input/output logic type inputs max voltage w/o damage loading inh (inhibit) em (enable bits1-8) el (enable bits 9-16) s (control transformer) bw (bandwidth) resolution control 10-bit 12-bit 14-bit 16-bit signal input characteristics resolver z in single ended z in differential z in each line-ground common mode range max voltage w/o damage direct input signal type sin / cos voltage range max voltage w/o damage z in 11.8 vrms l-l 70k ohm 140k ohm 80k ohm 26 v peak 100 v transient 2.0 vrms l-l 2 vrms nom, 2.3 vrms max 15 v continuous, 110 v peak transient >20m ohm//10 pf voltage follower outputs parallel data cb (converter busy) u (direction) mc (major carry) bit (built-in-test) los ( loss-of-signal) drive capability 10, 12, 14, or 16 bits logic 0: 1 ttl load logic 1: 10 ttl loads high z: 10 a / 5 pf max natural binary angle, positive logic. 0.4 s to 0.7 s positive pulse; leading edge initiates counter update. logic 1 counts up, logic 0 counts down. logic 0 at mc. logic 0 for bit condition. logic 1 for los (1-3 a pull-up to +5 v). -1.6 ma at 0.4 v max 0.4 ma at 2.8 v min. analog outputs v (internal dc ref) vel (velocity) e (ac error) dynamic characteristics +5.5 v nom 50 mvrms per lsb of error 25 mvrms per lsb of error 12.5 mvrms per lsb of error 6.3 mvrms per lsb of error see table 5, velocity characteristics. 10-bit mode. 12-bit mode. 14-bit mode. 16-bit mode. see table 4, dynamic characteristics. logic 0 = 0.8 v max logic 1 = 2.0 v min -0.3 to 11 v -10 a max voltage options and minimum input impedance, balanced. sin and cos resolver signal referenced to converters internal dc ref voltage of +5.5 v.
introduction the rdc-19200 series are small, 40-pin tdip resolver-to-digital hybrid converters. as shown in the block diagram (figure 1), the rdc-19200 can be broken down into the following function- al parts: signal input option, converter, analog conditioner, power supply conditioner, and digital interface. signal input options in a resolver, shaft angle data is transmitted as the ratio of carri- er amplitudes across the terminals. the converter terminal to the rdc-19200 operates with the signals in the resolver format, sin q cos w t. figure 2 shows the resolver signals as a function of the angle q . the rdc-19200 accepts solid state resolver (11.8 vrms) and direct (2 vrms) inputs. the reference is a single- ended input with 100k ohm impedance. 2 v direct input option (rdc-19202) the direct inputs are transient protected voltage followers which accept 2 vrms resolver inputs. as shown in figure 3. a 2 v input from a resolver allows use of a lower reference voltage. this lowers oscillator cost and allows a lower power reference oscillator. internal dc reference voltage (v). this internal voltage is not required externally for normal opera- tion of the converter. it is used as the internal dc reference com- mon with the direct input option. it is nominally +5.5 v and is pro- portional to the +15 vdc supply. 11.8 v resolver input option (rdc-19200) the 11.8 v resolver inputs are true differential inputs with high ac and dc common mode rejection (see figure 4). input impedance is maintained with power off. the recurrent ac peak + dc common mode voltage should not exceed 26 v peak; max- imum transient peak voltage should not exceed 100 v. 3 table 1. rdc-19200 specifications (continued) parameter value description power supply characteristics nominal voltage and range max voltage w/o damage max current -18 v 15 ma +8 v 10 ma +18 v 25 ma +15 vdc 5% +5v dc 10% -15 vdc 5% note: when analog outputs are not required, ground -15 v (pin 36). temperature ranges operating storage 0c to +70c -40c to +120c physical characteristics size weight 1.14 x 2.02 x 0.23 inches (28.96 x 51.3 x 5.84 mm) 0.6 oz (13 g) 40-pin tdip 30 150 210 330 360 q (degrees) ccw in phase with ref of converter and r2-r1 of cx. 0 s2-s4 = v cos q max s1-s3 = -v sin q max - v max + v max 60 120 240 300 +s voltage follower buffer - + 3 +sin rdc-19202 converter +c - + 2 +cos 1 2 v rms v figure 2. resolver signals figure 3. rdc-19202 direct input option -(2 v) standard resolver control transmitter (rx) outputs as a function of ccw rotation from electrical zero (ez) with r2-r4 excited. note 1: available for rdc-19202 (2v unit) only.
resistor programming for non-standard input voltages when applying voltages greater than 2 vrms, a simple voltage divider can be used to attenuate both the sin and the cos inputs. since the converter inputs are voltage followers, there will be no loading on the resistor dividers (see figure 5). the 11.8 v resolver input conditioner consists of two differential amplifiers. the 11.8 v input is scaled down to 2 v. when apply- ing resolver inputs greater than 11.8 v, four resistors, one in series with each input line, can be used to scale down the volt- age (see figure 6). converter operation as shown in figure 1, the converter section of the rdc-19200 contains a high accuracy control transformer, demodulator, error processor, voltage-controlled oscillator (vco), up-down counter, zero-set timing, and reference conditioner. the converter pro- duces a digital angle f which tracks the analog input angle q to within the specified accuracy of the converter. the control transformer performs the following trigonometric computation: sin( q - f) = sin q cos f - cos q sin f where: q is angle theta, representing the resolver shaft position f is digital angle phi, contained in the up/down counter. the tracking process consists of continually adjusting f to make ( q - f) ? 0, so that f will repeat the shaft position q. the output of the demodulator is an analog dc level proportion- al to sin( q - f). the error processor receives its input from the demodulator and integrates this sin( q - f) error signal which then drives the vco. the vcos clock pulses are accumulated by the up/down counter. the velocity voltage accuracy, linearity and off- set are determined by the quality of the vco. functionally, there are two stages of integration which makes the converter a type ii tracking servo. in a type ii servo, the vco always settles to a counting rate which makes the d f/ dt equal to d q/ dt without lag. the output data will always be fresh and available as long as the maximum track- ing rate of the converter is not exceeded. the reference conditioner is a comparator that produces the square wave reference voltage which drives the demodulator. it is single-ended ground-based with an input of z of 100k ohms min, 110k ohms nom, resistive. 4 + - v 12k 12k +s 70.8k 3 1 s1 s3 converter rdc-19200 resolver conditioner + - v 12k 12k +c 70.8k 2 4 s4 s2 70.8k 70.8k 11.8 v rms s3 s1 s2 s4 r1 r2 r4 r3 3 2 1 sin cos v rdc-19202 s3 r1 3 s3 rdc-19200 s1 r2 1 s1 s2 r3 2 s2 s4 r4 4 s4 figure 4. resolver input option - (11.8 v) figure 5. input resistor scaling - (2 v) figure 6. input resistor scaling - (11.8 v) input v oltage l-l = r1 + r3 2 v r3 notes: (1) r1 = r2; r3 = r4 to 0.1% match. (2) r1 + r3 and r2 + r4 should be as high as possible to minimize resolver loading. r + 70.8k = input v oltage l-l 70.8k 11.8 v notes: (1) input voltage l-l is greater than 11.8 v. (2) r = r1 = r2 = r3 = r4 to 0.1% match.
minimizing errors due to quadrature in those applications where highest accuracy is needed, the ref input can be phase shifted by adding a capacitor in series with the ref input (pin 40) to add a phase lead equal to the nominal phase lead of the resolver input. to determine the capacitors value, see figure 7. speed voltage = (rotational speed/carrier freq) * f.s. signal where: speed voltage is the quadrature due to rotation. rotational speed is the rps (rotations per second) of the resolver. carrier frequency is the ref in hz. analog conditioner the analog conditioner section performs three functions. it con- verts analog ground from 5.5 v to 0 v, provides a gain of 2 for ac error (e) and a gain of 2.2 for velocity (vel) the velocity scaling sensitivity can be increased with an external resistor. refer to vel programming section for more information. power supply conditioner the power supply conditioner lowers the internal power supply voltage to the custom cmos chip to +11 v from the +15 v sup- ply. the +11 v will track the +15 v. internal analog ground is one half of 11 v or +5.5 v, nom. digital interface the digital interface circuitry performs three main functions: 1. latches the output bits during an inhibit (inh) command allowing stable data to be read out of the rdc-19200. 2. furnishes parallel tri-state data formats. 3. acts as a buffer between the internal cmos logic and the external ttl logic. in the rdc-19200, applying an inhibit (inh) command will lock the data in the output transparent latch without interfering with the continuous tracking of the converters feedback loop. therefore, the digital angle f is always updated, and the inh can be applied for an arbitrary amount of time. the inhibit transparent latch and the 50 ns delay are part of the inhibit cir- cuitry. for further information, see the inhibit (inh, pin 9) para- graph. the bit detect circuitry monitors the error level (d) from the demodulator and the los (loss-of-signal) detector senses dis- connected resolver inputs. logic input/output the digital angle outputs are buffered and provided in a two-byte format. the first byte contains the msbs bits (1-8) and is enabled by placing em (pin 10) to a logic 0. depending on the user-pro- grammed resolution, the second byte contains the lsbs and is enabled by placing el (pin 11) to a logic 0. the second byte will contain either bits 9-10 (10-bit resolution), bits 9-12 (12-bit reso- lution), bits 9-14 (14-bit resolution) or bits 9-16 (16-bit resolu- tion). all unused lsbs will be at logic 0. table 2 lists the angu- lar weight for the digital angle outputs. the digital angle outputs are valid 150 ns after em or el are acti- vated with a logic 0, and are high impedance within 100 ns, max, 5 v 10k va 100k 40 c ref rdc-19200 100 pf figure 7. phase shifting the ref input note: choose c such that the v a to ref phase lead is equal to the resolver to ref phase lead plus 9 s. quadrature voltages in a resolver, quadrature voltages are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. a digital position error will result due to the interaction of this quadrature voltage and a reference phase shift between the converter signal and reference inputs. the magnitude of this error is given by the following formula: magnitude of error = (quadrature voltage/f.s. signal) * tan ( a ) where: magnitude of error is in radians. quadrature voltage is in volts. full scale signal is in volts. a = signal to ref phase shift. an example of the magnitude of error is as follows: let: quadrature voltage = 11.8 mv let: f.s. signal = 11.8 mv let: a = 6 then: magnitude of error = 0.35 min ? 1 lsb in the 16 bit. note: quadrature is composed of static quadrature which is specified by the resolver supplier plus the speed voltage which is determined by the following formula:
after el and em are set to logic 1. both enables are internally pulled up to +5 v by -10 a max current sources. digital angle output timing the digital angle output is 10, 12, 14 or 16 parallel data bits. all logic outputs are short-circuit proof to ground and +5 v. the cb output is a positive, 0.4 to 0.7 s pulse. the digital output data changes approximately 50 ns after the leading edge of the cb pulse because of an internal delay (shown in figure 1). data is valid 0.2 s after the leading edge of cb (see figure 8). the angle is determined by the sum of the bits at logic 1. the latch will not lock until the cb pulse is over. the purpose of the 50 ns delay is to prevent a race condition between cb and inh where the up-down counter begins to change as an inh is applied. an inh input, regardless of its duration, does not affect the con- verter update. a simple method of interfacing to a computer asynchronous to cb is: (1) apply inh (2) wait 0.3 s, min (3) transfer the data (4) release inh as long as the converter maximum tracking rate is not exceeded there will be no velocity lag in the converter output, although momentary acceleration errors remain. if a step input occurs, as when the power is initially applied, the response will be critically damped. figure 10 shows the response to a step input. after initial slewing at the maximum tracking rate of the converter, there is one overshoot (which is inherent in a type ii servo). the overshoot settling to a final value is a function of the small signal settling time. data transfers digital output data from the rdc-19200 can be transferred to 8- bit and 16-bit bus systems. for 8-bit systems, the msb and lsb bytes are transferred sequentially (see figures 11 and 12). for 16-bit systems, all bits are transferred at the same time ( see figures 13 and 14). 6 depends on d f /dt 0.4-0.7 m s cb 0.2 m s max data valid 1.22 m s min data valid 0.3 m s max asynchronous to cb inh figure 8. cb timing overshoot small signal settling time max slope equals tracking rate ( slew rate ) q 2 q 1 figure 9. inhibit timing figure 10. response to step input table 2. digital angle outputs bit deg/bit min/bit 10,800 5,400 2,700 1,350 675 387.5 168.5 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 180 90 45 22.5 11.25 5.625 2.813 1.405 0.7031 0.3516 0.1758 0.879 0.439 0.0220 0.0110 0.0055 1 (msb all modes) 2 3 4 5 6 7 8 9 10 (lsb 10-bit mode) 11 12 (lsb 12-bit mode) 13 14 (lsb 14-bit mode) 15 16 (lsb 16-bit mode) note: em enables the 8 msbs and el enables the lsbs. inhibit (inh, pin 9) when an inhibit (inh) input is applied to the rdc-19200, the output transparent latch is locked, causing the output data bits to remain stable while data is being transferred (see figure 9). the output data bits are stable 0.3 s after the inh is driven to logic 0. a logic 0 at the t input of the inhibit transparent latch latches the data, and a logic 1 applied to t allows the bits to change. this latch also prevents the transmission of invalid data when there is an overlap between cb and inh. while the counter is not being updated, cb is at logic 0 and the inh latch is transparent; when cb goes to logic 1, the inh latch is locked. if cb occurs after inh has been applied, the latch will remain locked and its data will not change until cb returns to logic 0; if inh is applied during cb,
7 rc-19200 8-bit bus (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 (lsb) bit 16 d7 d6 d5 d4 d3 d2 d1 d0 el em inh rdc-19200 16-bit bus (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 (lsb) bit 16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 el em inh inh data 1-8 valid data 9-16 valid 300 ns min 150 ns min 100 ns max 150 ns min 100 ns max el em inh data 1-8 valid 300 ns min 150 ns min 100 ns max em, el figure 11. 8-bit data transfer figure 13. 16-bit data transfer figure 12. 8-bit data transfer timing figure 14. 16-bit data transfer timing
programmable resolution resolution is controlled by two logic inputs, a and b (see table 3). the resolution can be changed during converter operations so the appropriate resolution and velocity dynamics can be changed as needed. to ensure that a race condition does not exist between counting and changing the resolution, inputs a and b are transferred through the latch internally on the trailing edge of cb (see figure 15). faster settling time using bit to reduce resolution since the rdc-19200 has higher precision in the higher resolu- tion mode and faster settling in the lower resolution modes, the bit output can be used to program the rdc-19200 for lower res- olution, allowing the converter to settle faster for step inputs. high precision, faster settling can therefore be obtained simulta- neously and automatically in one unit. when the resolution is changed, the vel scaling is also changed. since the vel output is from an integrator with a capacitor feedback, the vel voltage cannot change instanta- neously. therefore, when changing resolution while moving, there will be a transient with a magnitude proportional to the velocity and a duration determined by the converter bandwidth (see figure 22.) major carry (mc, pin 32) major carry is used with direction output (u) for multi-turn appli- cations. this signal is similar to the popular msi four bit up-down counter co (carry out), that is, it is normally high and goes low for all 1s when counting up or all 0s when counting down. see figure 16 for a typical interconnection. direction output (u, pin 31) direction output (u) timing is shown in figure 17. it is a logic 1 to count up and logic 0 for down. the logic level at (u) is valid at least 0.5 s before and at least 20 ns after leading edge of cb. system self-test the rdc-19200 provides two useful logic outputs for systems self-test, bit and los. built-in-test (bit, pin 29) the built-in-test output (bit) monitors the level of error from the demodulator (d). d represents the difference in the input and output angles and ideally should be zero. if it exceeds approxi- mately 65 lsbs ( of the selected resolution), the logic level at bit will change from a logic 1 to logic 0. this condition will occur dur- ing a large step and reset after the converter settles out. bit will also change to logic 0 for an over-velocity condition because the converter loop cannot maintain input-output sync, or if the con- verter malfunctions where it cannot maintain the loop at a null. loss of signal (los, pin 28) the loss of signal (los) output is used for system safety. the los output changes from logic 0 to 1 if both resolver inputs are disconnected. with disconnected resolver inputs unpredictable converter performance occurs. if the los signal is used with the 2 v direct input option, connect a 10m ohm resistor from +s to v and from +c to v. this will insure that if the input resolver signal opens, the input pin will go to v volts. 8 table 3. resolution control b (pin 8) a (pin 7) resolution 0 0 1 1 0 1 0 1 10-bit 12-bit 14-bit 16-bit note: all unused digital output data bits are at logic 0 a,b valid 0 m s min cb 0.1 m s min up/down counter c0 c1 mc u cb ut rdc-19200 4 bits turns counting direction (u) 0.5 m s min major carry mc don't care up count down count 20 ns min 0.5 m s min 0.5 m s min 0.5 m s min cb 0.5 m s min figure 16. turns counting connection diagram figure 17. direction output (u) timing figure 15. resolution control timing notes: (1) for the 4 bit up/down counter, use 74ls169b (ttl) or 4516 (cmos). (2) u = up/down line, logic 1 counts up. (3) t = toggle line, counts on positive edge.
programmable bandwidth (bw, pin 5) either low or high bandwidth can be selected by using the bw logic input. a logic 0 applied to bw selects low bandwidth (130 hz nom), while a logic 1 selects high bandwidth (530 hz nom). bandwidth can be changed during converter operation. bandwidth and the acceleration constant (ka) can be deter- mined from the following formulas: closed loop bandwidth (hz) = ? 2 a /p ka = a 2 see dynamic characteristics table 4 and figures 25 to 27 for values. 9 table 4. dynamic characteristics parameter units high bandwidth low input frequency tracking rate bandwidth, cl ka a 1 ** a 2 ** a** b** acc-1 lsb lag settling time resolution 1-6 800 530 1.4m 8 178 1200 600 512k 10 10 khz rps? hz 1/sec 2 1/sec 1/sec 1/sec 1/sec /sec 2 msec bits 2-6 50 * * * * * * 32k 30 14 * 200 * * * * * * 128k 15 12 .36-6 200 130 90k 2 45k 300 150 32k 40 10 nr 12.5 * * * * * * 8k 75 16 2-6 3.2 * * * * * * 500 300 16 * 12.5 * * * * * * 2k 120 14 * 50 * * * * * * 500 300 12 control transformer mode (s, pin 6) the converter will function as a control transformer (ct) by placing s (pin 6) to logic 0. in the ct mode the digital inputs are double buffered, em is redefined as lm, el is redefined as ll and inh becomes la (see figures 19 and 28). figure 18 shows ct mode timing for a two byte transfer. the ct mode is used when the ac error (e) is needed to drive an external control loop by the difference angle of the resolver input and the digital input. it is also used for presettling the con- verter to a specific angle to reduce the step response time. tw tsu tw th th tsu tsui thui (la) inh s = 0 data in (lm) em (ll) el high accuracy control transformer demodulator power supply conditioner sin ( q - f ) bit detect loss of signal detector 16 bit ct transparent latch 29 bit 40 ref 39 e 9 la(inh) 8 7 ab 1-4 resolver input 12-19 1-8 34 +15 v resolution control diff gain of 2 16 bit u-d counter (set mode) signal input gain reference conditioner 28 los sin q cos q digital angle f e +15 v -15 v 20-27 9-16 11 ll(el) 10 lm(em) +11 v +5.5 v d ?rps (revolutions per second) maximum * same as value to left ** see figure 25 for definition of a 1 , a 2 , a, and b figure 18. ct mode timing - two byte transfer, double buffered figure 19. control transformer block diagram notes: (1) tw = 100 ns min (pulse width) 1 - data held in latch th = 50 ns min (hold time) 0 - latch is transparent thui = 0 ns min (hold time inhibit) tsu = 0 ns min (setup time) (3) (la) inh is latch control tsui = 300 ns min (setup inhibit) for ct latch, (2) when s is low: 1 - latch is transparent (lm) em is latch control for msb byte, 0 - data held in latch. (ll) el is latch control for lsb byte,
analog outputs the analog outputs are ac error (e) and velocity (vel). if the analog outputs are not required, ground -15 v (pin 36). ac error (e, pin 39) ac error out (e) is used in ct mode. the ac error is propor- tional to the difference between the resolver input angle q and the digital angle f , ( q - f ), with a scaling of: 50 mvrms/lsb (10-bit mode) 25 mvrms/lsb (12-bit mode) 12.5 mvrms/lsb (14-bit mode) 6.3 mvrms/lsb (16-bit mode) the error is positive if it is in phase with the reference and neg- ative if it is out of phase with the reference. the e output can swing 10 v peak min with respect to ground when the voltage level of the 15 v power supplies are 15 v. the output level range changes proportionally with the power supply level. velocity (vel, pin 38) the velocity output (vel, pin 38) is a dc voltage proportional to angular velocity d q /dt. the velocity is the input to the voltage- controlled oscillator (vco), as shown in figure 1. its linearity and accuracy is dependent solely on the linearity and accuracy of the vco. the maximum vel output can swing 10 v min with respect to ground when the voltage level of the 15 v power supplies are 15 v. the output level range changes proportionally with the power supply level. the analog output vel characteristics are listed in table 5. the vel output has the dc tachometer quality specifications such that it can be used as the velocity feedback in servo appli- cations. velocity programming (vel prog, pin 37) the velocity output scale factor can be increased by connecting an external resistor (r) from vel prog, pin 37, to ground. by scaling up the output, the noise and offset will increase propor- tionally. the value of r can be determined by the following for- mula: r = 10 x b/a 1 - b/a where: r = external resistor in k ohms a = specified voltage scaling (rps/volt) b = desired voltage scaling (rps/volt) to determine a refer to table 6, voltage scaling. dynamic performance a type ii servo loop (kv = ) and very high acceleration con- stants give the rdc-19200 superior dynamic performance as listed in table 1. small signal step response figure 20 illustrates the small signal step response (100 lsb step) for low and high bandwidth for the four resolutions. large signal step response figure 21 illustrates the large signal step response (179 step) for low and high bandwidth for the four resolutions. bit output reduces settling time by using the bit output together with the a and b inputs, the large signal settling time may be significantly reduced. fig- ure 22 shows the connections required for bit, a, and b and the resultant settling for the different resolution modes. velocity response a filter on the vel output will, for a step input in velocity, elimi- nate the velocity overshoot (normally critically damped) and filter carrier frequency ripple. figure 23 shows the vel output with and without a filter for low and high bandwidths. the vel filter is shown in figure 24. 10 vel prog 37 rdc-19200 r table 6. velocity output voltage scaling (rps/volt) bw 10-bit 12-bit 14-bit 16-bit high 80 20 5 1.25 low 20 5 1.25 0.32 15 200 2 2 40 50 3 10 10 100 1 1 15 25 - 13 rps/v % ppm/c 5 % output mv v/c k ohms v polarity voltage scaling scale factor scale factor tc reversal error linearity zero offset zero offset tc load output voltage max typ unit parameter table 5. velocity output characteristics positive for increasing angle see table 6
11 0 100 10 20 30 40 50 output (lsbs) time (ms) figure 20. small signal step response (100 lsb step) low bandwidth - 10-bit mode 0 100 10 20 30 40 50 output (lsbs) time (ms) low bandwidth - 12-bit mode 0 100 10 20 30 40 50 output (lsbs) time (ms) low bandwidth - 14-bit mode 0 100 10 20 30 40 50 output (lsbs) time (ms) low bandwidth - 16-bit mode 0 100 246810 output (lsbs) time (ms) high bandwidth - 10-bit mode 0 100 4 8 12 16 20 output (lsbs) time (ms) high bandwidth - 12-bit mode 0 100 246810 output (lsbs) time (ms) high bandwidth - 14-bit mode 0 100 20 40 60 80 100 output (lsbs) time (ms) high bandwidth - 16-bit mode
12 figure 21. large signal step response (179 step) 0 60 120 180 10 20 30 40 50 output angle (degrees) time (ms) low bandwidth - 10-bit mode 0 60 120 180 10 20 30 40 50 output angle (degrees) time (ms) low bandwidth - 12-bit mode 0 60 120 180 20 40 60 80 100 output angle (degrees) time (ms) low bandwidth - 14-bit mode 0 60 120 180 20 40 60 80 100 output angle (degrees) time (ms) low bandwidth - 16-bit mode 0 60 120 180 12345 output angle (degrees) time (ms) high bandwidth - 10-bit mode 0 60 120 180 246810 output angle (degrees) time (ms) high bandwidth - 12-bit mode 0 60 120 180 10 20 30 40 50 output angle (degrees) time (ms) high bandwidth - 14-bit mode 0 60 120 180 20 40 60 80 100 output angle (degrees) time (ms) high bandwidth - 16-bit mode
13 figure 22. using bit to reduce settling time (179 step) 0 60 120 180 10 20 30 40 50 output angle (degrees) time (ms) low bandwidth - 12- to 10-bit mode 0 60 120 180 10 20 30 40 50 output angle (degrees) time (ms) low bandwidth - 14-to 10-bit mode 0 60 120 180 10 20 30 40 50 output angle (degrees) time (ms) low bandwidth - 16- to 10-bit mode 0 60 120 180 246810 output angle (degrees) time (ms) high bandwidth - 12- to 10-bit mode 0 60 120 180 246810 output angle (degrees) time (ms) high bandwidth - 14-to 10-bit mode 0 60 120 180 246810 output angle (degrees) time (ms) high bandwidth - 16- to 10-bit mode bit a b bit a b bit b a bit b a bit a b bit a b
14 figure 23. vel output with and without filter vel filtered (low bw) r=100k vel c = 0.033 m f vel filtered (high bw) r=100k vel c = 0.0082 m f t = rc = 1/a t = rc = 1/a figure 24. vel output filters 10 20 30 40 50 voltage (1 v/div) time (ms) 0 low bandwidth - 12-10-bit mode 10 20 30 40 50 voltage (1 v/div) time (ms) 0 low bandwidth - 14-10-bit mode 10 20 30 40 50 voltage (1 v/div) time (ms) 0 low bandwidth - 16-10-bit mode 4 8 10 12 16 voltage (1 v/div) time (ms) 0 high bandwidth - 12-10-bit mode 4 8 10 12 16 voltage (1 v/div) time (ms) 0 high bandwidth - 14-10-bit mode 4 8 10 12 16 voltage (1 v/div) time (ms) 0 high bandwidth - 16-10-bit mode before filter after filter before filter after filter before filter after filter before filter after filter before filter after filter before filter after filter
transfer functions the dynamic performance of the converter can be determined from its transfer function block diagram (figure 25) and open and closed loop bode plots (figures 26 and 27). table 4 lists the parameters relating to the rdc-19200s dynamic character- istics for different resolution and bandwidth modes. accuracy and resolution table 7 lists the total accuracy including quantization for the various resolution and accuracy grades. 15 error processor resolver input converter transfer function g = where: 2 a = a a 1 2 velocity out digital position out ( f ) vco ct s a + 1 1 b s s + 1 10b h = 1 2 s a + 1 b 2 s s + 1 10b + - e a 2 s figure 26. open loop bode plot figure 27. closed loop bode plot -12 db/oct 4 ba 2a -6 db/oct 10b w (rad/sec) 2a 2 2 a w (rad/sec) closed loop bw (hz) = 2 a p table 7. accuracy/resolution rdc-19200 series model no. accuracy 12 bit 10 bit 14 bit 16 bit rdc-19202-304 rdc-1920x-303 rdc-1920x-302 rdc-19202-301 2 + 1 lsb 3 + 1 lsb 4 + 1 lsb 8 + 1 lsb 7.3 8.3 9.3 13.3 23.1 24.1 25.1 29.1 3.3 4.3 5.3 9.3 2.3 3.3 4.3 8.3 rdc-19200 applications using the rdc-19200 in the ct mode the ct mode can be applied in servo systems, as shown in fig- ure 28. in this application, changes in position are commanded by the computer through signals fed to the ct. the ct then dri- ves the motors through dc power amplifiers. multi-turn applications - use of major carry (mc, pin 32) refer to major carry paragraph on page 8 for details. using the rdc-19200 as an r/d with vel to stabilize position loop figure 29 illustrates a typical use of an rdc-19200 connected as an r/d using the vel output to stabilize the position loop. figure 25. transfer function block diagram note: see table 4 for values of a1, a2, and b.
rdc-19200 to ibm pc/xt/at theory of operation 1. the port address where the rdc-19200 is located is hard wired with jumpers into the 74ls688 address decoder. this address is hex 300 through 303 and is reserved for prototype cards. 2. address line a1 selects the upper or lower of the rdc-19200 to be placed on the bus. when a1 is high, bits 1-8 are selected. 3. address line a0 sets and resets the rdc-19200 inhibit line. when a0 is low, the inhibit command inh is invoked. 4. to read the output of the rdc-19200, perform the following: a. send address hex 302 to inhibit the rdc-19200 (hold data stable) and place bits 1-8 on the bus. read and store data on d0 to d7. b. send address 300 hex to keep the rdc-19200 in the inhibit mode and place bits 9-14 on the bus. read and store data on d0 and d7. c. read address 301 hex or 303 hex to release the rdc-19200 from the inhibit mode and prepare for the next measurement. no valid data will be on the bus during this command. 5. since the output data is not valid until 0.5 s after the inhib- it command is invoked, the i/o ready line is held low for this period of time. when i/o ready returns to the high level, the data on the bus reads on the next negative clock edge. 16 amp demodulator m computer rdc-19200 as a ct ref resolver e s figure 28. ct mode application amp computer r/d con- verter ref source resolver d/a vel figure 29. r/d with vel to stabilize position 500 nsec min pulse latch read data valid address clk ale addr i/o ready i/o r out out out in out figure 30. pc application - i/o read cycle timing interfacing the rdc-19200 with an ibm pc/xt/at ? the rdc-19200 can be connected to an ibm pc/xt/at through the ibm pc bus located at address hex 300 through 303. this location is reserved by the pc for prototype cards. figure 31 illustrates the connection to the ibm pc bus; figure 30 illus- trates the timing considerations for the interface.
17 bit 16(lsb) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 q0 q1 q2 q3 q4 q5 q6 q7 a9 a8 a7 a6 a5 a4 a3 a2 y1 y2 y3 y4 y5 y6 y7 y8 ibm bus bus driver 74ls465 address decoder 74ls688 address selection jumpers 74ls374 74ls467 rdc-19200 74ls121 q a2 inh el em q clk d y1 y2 y3 y4 a1 a2 a3 a4 g g p=q ale i/o read g a1 a0 i/o ready 3 state buffer 500 nsec min pulse p0 p1 p2p p3 p4 p5 p6 p7 figure 31. rdc-19200 to pc connection diagram
18 table 8. rdc-19200 pin functions pin no title i / o function 1 s1(r)v(x) i (r) = 11.8 v resolver input; (x) = v return (do not gnd). 2 s2(r)+c(x) i (r) = 11.8 v resolver input; (x) = 2 v cos input. 3 s3(r)+s(x) i (r) = 11.8 v resolver input; (x) = 2 v sin input. 4 s4(r) i (r) = 11.8 v resolver input. 5 bw i bandwidth. logic 1 for high bw (530 hz); logic 0 for low bw (130 hz). 6 s i control transformer set. logic 1 for normal tracking; logic 0 for ct operation. used when ac error (e) is needed to drive external control loop by the difference angle of the resolver input and the digital input and for presetting the converter to a specific angle to reduce the step response time. 7 8 a b i resolution control. changes resolution during converter operation to 10, 12, 14 or 16 bit, depending on logic level. b a resolution 0 0 10-bit 0 1 12-bit 1 0 14-bit 1 1 16-bit 9 inh i inhibit. logic 0 prevents digital output bits from changing. 10 em i enable msbs logic 0 enables digital output bits 1-8. logic 1 disables these bits. 11 el i enable lsbs logic 0 enables digital output bits 9-16. logic 1 disables these bits. 12 1 o digital output bit 1 (msb all modes). 13 2 o digital output bit 2. 14 3 o digital output bit 3. 15 4 o digital output bit 4. 16 5 o digital output bit 5. 17 6 o digital output bit 6. 18 7 o digital output bit 7. 19 8 o digital output bit 8. 20 9 o digital output bit 9. 21 10 o digital output bit 10 (lsb- 10-bit mode). 22 11 o digital output bit 11. 23 12 o digital output bit 12 (lsb - 12-bit mode). 24 13 o digital output bit 13. 25 14 o digital output bit 14 (lsb - 14-bit mode). 26 15 o digital output bit 15. 27 16 o digital output bit 16 (lsb - 16-bit mode). 28 los o loss of signal. used for system safety, the los output changes from logic 0 to 1 if both resolver inputs are disconnected. 29 bit o built-in-test. monitors level of error (d) and will change to logic if it exceeds 65 bits, approx. also logic 0 for an over velocity condition. 30 cb o converter busy indicates digital output update. 31 u o direction. logic 1 to count up; logic 0 to count down. 32 mc o major carry. used for turns counting applications; normally high; goes low for all 1s when counting up or all 0s when counting down. 33 +5 v i supply voltage. 34 +15 v i supply voltage. 35 gnd - ground. 36 -15 v i supply voltage. 37 vel prog i velocity programming. increases output scale factor with external resistor (r) from vel prog, pin 37 to ground. 38 vel o velocity. dc voltage proportional to angular velocity. 39 e o ac error. used in ct mode; e is proportional to the difference between the resolver input angle q and the digital output angle f ( q - f ). 40 ref i ac reference input. used to drive internal demodulator.
19 reference oscillator parallel data rdc-19200 can interface with 8 or 16 bit microprocessor stator rotor s3 s1 s2 s2 s1 s3 el em r2 r1 lo hi ref cb vel inh s2 s2 reference oscillator parallel data rdc-19202 can interface with 8 or 16 bit microprocessor stator rotor sin cos v s4 s2 s3 el em r2 r1 lo hi ref cb vel inh s1 figure 32. rdc-19200 resolver connection - (11.8 v) figure 33. rdc-19202 direct connection - (2 v)
20 k-08/99-500 140 20 21 pin 1 denoted by orientation mark pin numbers for ref. only 1.14 max (28.96) 2.02 max (51.3) 0.23 max (5.84) 0.160 0.040 (4.06 1.02) 0.010 typ (0.25) 0.90 typ (22.86) 0.11 typ (2.79) 0.100 typ (2.54) 0.50 typ (1.27) 19 eq. sp. @0.100=1.900 tol. non cum typ (@2.54=48.26) 0.018 typ (0.46) 60/40 tin lead plated phosphor bronze 0.050 typ (1.27) dimensions are in inches (mm). figure 34.rdc-19200 mechanical outline connecting the rdc-19200 the rdc-19200 can be attached to a pc board using hand solder or wave soldering techniques. limit exposure to 300 c (572 f) max, for 10 seconds maximum. do not use vapor phase soldering as this product contains sn60 or sn62 solder which melts at 180 c (356 f). since the rdc-19200 series converters contain a cmos device, standard cmos handling procedures should be followed. sources of sockets for the rdc-19200 the following companies are sources of sockets for use with the rdc-19200 series. consult them for more information. aries electronics, inc. single in-line socket p.o. box 130 strip-line socket trenton avenue part no. 20-05511-11 frenchtown, nj 08825-0130 tel: 1-908-996-6841 http://www.arieselec.com circuit assembly corp. part no. ca-20-stl-xxxx-x 18 thomas street irvine, ca 92618-2777 tel: 714-855-7887 http://www.ca-online.com ordering information rdc-1920x-30x accuracy: 1 = 8 min + 1 lsb (1) (12 lsb?s differential linearity) 2 = 4 min + 1 lsb (8 lsb?s differential linearity) 3 = 3 min + 1 lsb (4 lsb?s differential linearity) 4 = 2 min + 1 lsb (1) (4 lsb?s differential linearity) configuration: 0 = 11.8 v, 2% linearity 2 = 2 v, 2% linearity the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. printed in the u.s.a. note 1. available for rdc-19202 only. note 2. differential linearity is x lsb in the 16th bit. ilc data device corporation registered to iso 9001 file no. a5976 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7389 or 7413 headquarters - tel: (631) 567-5600 ext. 7389 or 7413, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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